So, I wanted a logic analyzer, and I wanted it cheap. After hearing about the Saleae Logic I was excited, after all what is a logic analyzer but a pile of IO and some nice software. The thing is, the rate at which you may want to take samples can be much greater than the transfer speed of, say, USB 2.0. The cool thing about the Saleae Logic, USBEE, Braintechnology USB-LPS, and presumably others is that they use the Cypress FX2 chip. The main benefit of this chip is that it has an enormous 4 Kilobyte FIFO buffer attached to ports B and D. That means it can take a huge number of samples really fast. That chip is really weird, well, it’s the first I’ve heard of having to push firmware to a chip upon plugging it into a computer. This means that any software that wants to use a peripheral based on this chip can simply push fresh code on boot to the processor, allowing firmware upgrades to be as easy as software upgrades for the client software. This also means that any software is free to push it’s code to any peripheral and try to use it. This could be problematic if you end up trying to output into a one-way buffer chip or anything else since the associated hardware could differ wildly from devices utilizing this chip. The way around this is to have an I2C EEPROM that has the usb Vid:Pid on it, allowing authentication of peripherals to the software. This method can pragmatically be used for protection, or used for DRM (I think you see where this is going).
There is an open source logic analyzer project known as sigrok that has a client for many different logic analyzers, and a sub-project fx2lafw which is a firmware for FX2 based logic analyzers. They have a wealth of information about various logic analyzers, especially the FX2 variants. Some of the stuff I found most interesting was the details on which eeprom and buffer each device uses. Since I am planning on using this chip as a logic analyzer, and as such will be connecting it to foreign/unknown hardware I think an input buffer is pretty important. I went with the ST DVIULC6-4SC6 because that’s what the Saleae used, it’s fantastically simple, it’s just a diode array used to tie any over voltages to the power rails, so you just tap it right on to your data lines, not through. The benefit of these is that they’re designed for ESD and can respond even with signals switching at up to 1.65Gb/s. Now the other thing the sigrok site has for input protection is series resistor values. Clamping diodes protect from voltage, but series resistors protect from current. While they don’t actually list the resistor values, they have detailed pictures with which you can actually read the smd markings… except the Saleae uses packages without markings <sigh> whatever, I used 4.7k 603 package ones between 2 pads on a standard perf board.
My original plan was to break out all 16 pins of the FIFO (prots B and D) so that I could have a 16 channel logic analyzer, but ST only samples one of each part and only had 2 variants of the ESD chip, so… I’ll do that later if I really want it. Now I just needed to figure out the EEPROM problem. I bought the Lcsoft CY7C68013A Mini Board off of ebay for ~$15 it comes with an EEPROM on it and a jumper to set the address of the chip, the problem is the chinese company used an EEPROM with 16bit memory addressing and put it at the address where the Saleae looks for an EEPROM, except the FX2 needs an EEPROM with 8bit addressing at that address, and the Saleae won’t look at the address where the FX2 will allow a 16bit addressed EEPROM. Basically, while they tried to create a knock off, they failed. I know they tried to create a knock off because I dumped the 24c128 they had on the board, it had the right USB Vid:Pid on it for the Saleae. Well, it’s fantastically easy to find EEPROMs of the required interface as they are used all the time as the DDC chip in any VESA compatible display (VGA, DVI, or HDMI ports each have one) to communicate to the computer what resolutions a monitor is capable of. There is a way to use the Cypress tools to reprogram the EEPROM if you don’t have any other tools to do it, but I just used my tl866cs, fantastic programmer (trying to upgrade it to a tl866a). I salvaged a few from the logic board of a long dead and smashed LCD, wrote them with the required bytes and voila! we have a Saleae Logic. but that’s not enough, oh no, I need to make this better than retail. How about making it also a USBEE ZX? well, kinda. I have yet to figure out what pins on the FX2 map to the Trigger and Clock on the USBEE ZX. Also, I have some sources that say the USBEE ZX is not as picky about the EEPROM type as the Saleae is. And I needed to solder a jumper from the board to the protoboard since 5v isn’t broken out on the headers (for the GND, 3.3v, 5v header). So, I grabbed another EEPROM, burned in some new Vid:Pid bytes and hey! it works too!
Fabrication took place in my signature style: using whatever I had lying around and not bothering to etch a board. Don’t get me wrong, I can etch a board in a few hours with the tools at hand, I just didn’t feel like it. “But they’re surface mount chips” I hear you cry. “But I don’t care” I respond. Some people invest in rework stations and reflow ovens, all I need is a really, really fine tip on my iron. Not for this project though, a regular fat tip will do just fine. “How can you solder those chips down? the pin pitch isn’t right”. Ok, fine, scrape off 2 circles of copper and straddle it with the EEPROMs tack the corners and the 2 center pins on each side aren’t soldered to the board. “But you have 2 EEPROMs…”. Do I even have to say this one? Stack them, wire all pins in parallel except the SDA line, switch that one with the jumper. “Ok, fine, but the SOT23-6 don’t stradle like that, ha!” Ok, fine, shave off half a pad, straddle the middle pin over that space. “Hey, you should get some 30 gauge kynar wire for that, works great”. I’d love some… oh, you’re not offering? well then, scrap 40pin IDE cable it is. Some fantastically cheap 0.1″ female headers from ebay (not breakaway, but at these prices I can sacrifice a pin every time I want to shorten them), scrap male headers from an old motherboard, and a jumper from a dead IDE CD drive, and a bit of nearly new protoboard, now I’ve got a logic analyzer.
8 channel logic analyzer + ground pin
jumper to select which EEPROM
in line resistor protection
diode clamp protection
GND, 3.3v, 5v header (on the USBEE)
Things I missed/messed up:
USBEE trigger and clock pins
ground pin should be on other side (to match Saleae)?
PORT D (remaining 8 pins for use with sigrok)
’C0-A9-08-05-00-84-23-00′. this is the VID:08A9 and PID:0005 for the USBee ZX device. ‘C0-25-09-81-38-1B-00-00’. This is the VID:0925 and PID:3881 for the Saleae device.
PORT B[0:7] => Saleae[purple:black] (I think that’s the correct order)