Northstar advantage replica PCBs (PIO/SIO/previews)

After having gotten the keyboards working on some Northstar Advantage computers the next step is clearly to start knocking off add-on cards.

From what I can tell every single one of these machines sold had a SIO, or Serial Input/Output card in slot 1. There’s a mode where you can boot from serial, but in order to do that it has to be in slot 3 and in synchronous mode for some reason. I haven’t gotten this mode working quite yet, but having an esp8266 translate between synchronous 2400baud serial and some wifi connected server with boot images on it would be super cool. From what I can tell these machines shipped with an 8251 USART chip, and the manual indicates configuring it to go as high as 19200 baud. The Intel datasheet for the 8251 indicates asynchronous operation only up to 9600 baud reliably. We found that to be true as there were glitches trying to send and receive data over an 8251 configured for greater than 9600 baud. When we switched to an 8251A those problems were reduced, and the datasheet for an 8251A does indeed show async operation up to 19200 baud.

I have replicated the serial card including the general trace layout and silk/copper text. It’s not exact to the perfect trace width or spacing, but it’s pretty close. The similarities are at least such that you can still use the original documentation to debug or modify the card. I have two versions, one that places the DB-25 port in the original location, and one that moves it so the ports I can get my hands on will line up properly (and I think this spacing is generally more standard).

As far as initial testing goes, I loaded up the computer and placed the card in slot 1 (the one closest to the power supply). Once booted, at the load screen I held control and hit c to put it in monitor mode. This way I can read and write individual ports as seen by the z80. Port $75 is the one that reads the ID from slot 1. The IDs are defined here:

Theoretically I should get an F7. Let’s look at the setup:

And what do we get?

Perfect, but how does this card return F7? Well, in binary F7 is 11110111, only bit 3 is zero. What does the schematic for the ID request line look like?

This is the only part of the schematic that matters. What it seems to mean is that when the /ID_REQ line goes low to read the ID of the board, all the data lines are pulled high except bit 3 which is driven to zero by the ID request signal itself. That’s a pretty clever way of doing it but it only allows one bit to be changed from the default $FF state (without diodes or other hardware).

The next card is the PIO card, or Parallel Input/Output card. I have never seen a real life example of one of these cards. In the manuals I found a schematic, a silk screen layout, a BOM indicating things like the connector polarity, and definitions of how to address and configure the card. This is pretty much enough to make a replica, the only thing I’m missing is the trace layout. Without that I can make a working replica, but not one that looks exactly like the original.

Pictured here are revisions 1 and 2, which represent my board design before and after I learned how to use ERC and DRC. I nade a simple error in the schematic that joined a bunch of nets that shouldn’t have been and I didn’t notice because I had no real trace layout to follow. I also decided to play with the silk screen on the back to label all the pins that you might care about and the default jumper configuration.

To read the ports on a given card you have to use this lookup table per slot. For slot 1 the reads and writes to the card go to ports $50-$5F

On the Parallel card the same port is used for input and output of a single byte, that being the 0th port of that range, so for our purposes that’s port $50 since I’m only using slot 1 for my testing.

This was tested with a dip switch block and set of 8 LEDs. I didn’t test the flag, ack, strobe, or spare lines, but I assume they all work as desired.

There is a series of reads showing me flipping the dip switch bits individually and as groups. The output commands are different, they take the form of OYYXX where YY is the byte to write and XX is the port to write it to. Testing the LEDs looked alright as well

Since my LEDs are wired inverted that’s all on, then every other one on, then flip the polarity of all of them. What about the ID byte?

That matches, but it uses two bits. $DB in binary is 11011011 where both bit 2 and bit 5 are zero. How does it do that?

This is the section of the circuit for the parallel card. When /ID_REQ goes low it enables the B part of the 74LS367 which connects only the B pins, in this case bits 2 and 5 are connected to ground. That explains how this board handles an ID byte with 2 bits changed from the default $FF.

Here’s a sneak peek of what my next board is:

I just finished the hard drive controller PCB in kicad. I’m not sure it’s actually perfect yet, but I’m going to be trying for a working replica soon-ish. I got to borrow a real one so let’s install it and check the ID byte on the real (but supposedly not functional) board

That is… not what the manual says it should be. Perhaps that’s part of the issue, let’s look at the relevant part of the schematic.

Hmm… This looks to be using the same trick as the SIO to define the ID byte as $FF but have the signal that checks for the byte flip one of the bits directly be reading itself back. That would give us BF alright, there’s nothing hooked to the zeroth bit to change the F to an E. Does this mean this aspect of the card is working and the documentation is wrong? Well, I have this in Kicad now, so let’s have a look at how I think the board is laid out (which admittedly is generated from the schematic but verified visually).

That’s the ID_REQ line on the right joining up with bit 6 on the left and the three chips that bit 6 touches. I’m inclined to believe that the HD5 board is supposed to actually return $BF, and not $BE as the documentation says. That being said now I get to delve into debugging this hard drive controller. Once I have it actually working I can order some PCBs of my own since I have a working version to check them against.

All my cards and some of the documentation for the northstar can be found here: https://github.com/abzman/Northstar-Advantage-Cards

Oh, and the 8088 coprocessor card gives an ID byte of $FB, ask me how I know…

[UPDATE]

Apparently there’s a northstar advantage emulator and its documentation indicates that BF is a valid ID byte for the hard drive controller: